Wordline clamps may reduce memory cell currents. FIG. 1 illustrates a circuit 10 implementing a conventional wordline clamp in a programmable logic device (PLD). The circuit 10 contains a transistor 12, a transistor 14, a transistor 16, a transistor 18 and a transistor 20. The transistor 12 has a source that receives an input signal I0 and a gate that receives a select signal SEL0. The drain of the transistor 12 is coupled to the gates of the transistors 14 and 16. Transistors 14 and 16 form a conventional inverting buffer. A signal ENABLE is presented to the gate of the transistor 18. The source of the transistor 14 is connected to a power supply voltage. The source of the transistor 14 and the drain of the transistor 16 are coupled together and the corresponding node between them is coupled to the source of the transistor 20. The source of the transistor 16 is coupled to the drain of the transistor 18. The source of the transistor 18 is coupled to ground. The drain of the transistor 20 presents an output signal ITB. The gate of the transistor 20 receives a reference voltage ITREF.
The input signal 10 is modulated at the output ITB by a reference voltage signal ITREF connected to the gate of the transistor 20. The transistor 20 is generally a high voltage NMOS pass gate. The output ITB can only rise to a threshold voltage below the gate voltage of the transistor 20. The gate voltage is generated by a complex reference circuit which acts to optimize operation(s) over process, temperature and voltage variations. However, the reference circuit adds complexity to the circuit. It is thus generally desirable to provide a relatively simple circuit, such as a voltage clamp, to control the output of a wordline in a memory circuit, and particularly a static random access memory (SRAM)circuit.